Improvement of the integration density of a semiconductor device has been achieved mainly by developing finer patterning of transistors therein. However, in a typical transistor of a planar type, the development of finer patterning inevitably reduces the gate length. This reduction of the gate length increases the sub-threshold current of the transistor due to a short channel effect. For prevention of the short channel effect, it is necessary to employ a countermeasure as by increasing the impurity concentration of the channel region of the transistor.
However, a higher impurity concentration of the channel region incurs the problem of increase of a junction leakage current. Although the junction leakage current scarcely causes a significant problem in a transistor used in a logic circuit, the junction leakage current incurs a serious problem in a transistor of a DRAM memory cell, considerably degrading the refresh characteristic thereof. Thus, as a method of preventing the short channel effect, it is not appropriate to increase the impurity concentration of the channel region, especially in a cell transistor of the DRAM device.
Techniques for preventing the short channel effect without increasing the impurity concentration of the channel region include one that forms a transistor in a three-dimensional structure, i.e. not in a two-dimensional structure, unlike the planar transistor.
A fin-type transistor (fin transistor) is known as one of the three-dimensional transistors. The fin transistor includes a semiconductor active area having a shape of fin extending perpendicularly to the surface of the semiconductor substrate on which the transistor is formed. The top and side surfaces of the fin are covered by the gate electrode of the transistor, whereby the effective channel width of the transistor is increased to secure a sufficient ON current therein. In addition, the configuration wherein the gate electrode covers the top and side surfaces of the fin provides a superior controllability by the gate electrode, which effectively suppresses occurrence of the short channel effect. Further, it is possible to reduce the channel width as viewed perpendicular to the substrate surface, while securing a sufficient ON current, without occurring of an insufficient depletion of the channel region during the OFF state thereof. This provides improvement in the sub-threshold current characteristic as well as reduction of the off-leakage current.
The fin transistor is described in the following patent publications:
JP-1993-218415A (Patent Publication 1);
JP-2002-118255A (Patent Publication 2); and
JP-2005-150742A (Patent Publication 3).
The present inventor conceived the problem of increased gate capacitance encountered with the fin transistor, as will be described hereinafter. The gate capacitance in the fin transistor may be reduced by forming an isolation area to encircle the fin active area of the transistor and forming a substantially planarized surface on which the gate electrode is formed, such as described in Patent Publication 2 (FIGS. 20 and 68) and Patent Publication 3, without forming the three-dimensional gate electrode. However, this structure incurs the problem of poor controllability of the source/drain diffused regions formed adjacent to the gate electrode. This problem will be described with reference to drawings.
FIG. 20A is a perspective view of a fin transistor, and FIGS. 20B and 20C are sectional views thereof taken along lines X-X and Y-Y in FIG. 20A. In FIG. 20A, a fin active area 12 is encircled by an isolation area 11 on a semiconductor (silicon) substrate 10. A gate electrode 13 extends across the active area 12, and includes a first portion opposing the top surface 12a of the active area 12, and a pair of second portions 14a and 14b each opposing the sidewall of the active area 12. A portion of the active area 12 encircled by the first and second portions of the gate electrode 13 configures a channel or channel region 12b of the transistor. Drain 20 and source 21 are formed in the active area adjacent to both ends of the channel region 12b. 
In FIG. 20B, slits 18 and 19 are provided adjacent to the isolation area 11. The slits 18 and 19 are filled with a polysilicon film 14 which configures the second portion of the gate electrode, or sidewall electrodes 14a, 14b. The fin channel region 12b encircled by the gate electrode 13 in three directions includes a top surface 12a, and side surfaces 18a, 19a. The gate electrode 13 has a two-layer structure including a polysilicon film 14 and a metallic film 15 formed thereon. A top insulation film 16 is formed on the metallic film 15. Since the most portion of the gate electrode 13 is located on the top surface of the isolation area 11 which includes therein a thick insulating film, the gate capacitance can be reduced in this structure.
In FIG. 20C, the gate electrode 13 including the polysilicon film 14 and metallic film 15 and the top insulation film 16 are formed on the active area 12 with an intervention of a gate insulation film (not illustrated). A sidewall insulation film 17 is also formed on the sidewall of the gate electrode 13. The drain 20 and source 21 are formed by ion implantation into the surface portion of the active area 12 by using the top insulation film 16 and sidewall insulation film 17 as a mask. After introduction of impurities into the source/drain regions, a heat treatment is generally conducted to diffuse the impurities. If the impurities are diffused to a depth larger than the depth denoted by “H” in FIG. 20B, the impurities existing below the gate electrode 13 reduce the effective channel length, which is denoted by L1 in FIG. 20C, and changes the designed threshold voltage, whereby a desired transistor characteristic cannot be obtained.
Patent Publication 1 describes a structure wherein the active area is not surrounded by the isolation area, and thus ion-implantation for the source/drain regions is performed also into an exposed side surface of the active area by a slanted implantation. However, as shown in FIG. 3 of the Patent Publication 1, depth of the diffused regions thus implanted is restricted by the location of the side surface of the adjacent active area, i.e., restricted by the width of the slit. A smaller width of the slit is incompatible with a larger depth of the diffused regions, thereby restricting the degree of finer patterning. In addition, it is not practical to form the structure of gate electrode being matched with the step difference formed in the active area, because the step difference may incur a significant amount of residuals after etching for the gate electrode.